1. Field of the Invention
The present invention relates to electromagnetic communications systems. More specifically, the present invention relates to direct digital synthesis (DDS) and direct digitization of radio frequency (RF) signals.
2. Description of the Related Art
For current and future applications, space based radars will require high performance at lightweight and small volume. For example, by the year 2008, such systems will be expected to handle multiple tasks such as Synthetic Aperture Radar (SAR), Ground Moving Target Indication (GMTI), Airborne Moving Target Indication (AMTI), Digital Terrain Elevation Detection (DTED), and other multi-intelligence (INT) functions. Current systems tend to be stove piped, narrowly focused and single functioned. In addition, payloads for these systems will be required to have weight densities on the order of 4 kg per square meter (3 times lighter than today""s systems) and volume compaction of about 1500:1 (typical compaction ratios are currently between 3 and 5 to 1). Potential customers have also stressed a need for all of these improvements at a lower cost than can be achieved today (in light of shrinking budgets).
Current space based radar systems incorporate consolidated receivers and exciters. These solutions are adequate for systems that do not require large numbers of independent phase centers (typically less than 8), do not need to perform multi-INT missions, do not need to weigh less than 12 Kg per square meter, do not need ultra-wide bandwidths, etc. Furthermore, current solutions for today""s receiver functions tend to cost about $1M per channel (for space qualified hardware) which would be unacceptable for systems requiring over 32 independent receivers for example. Thus, current hardware is expensive, bulky, heavy, relatively specialized and not suitable to meet tomorrow""s needs.
Hence, a need exists in the art for an improved system or method for receiving and exciting electromagnetic signals which is smaller, lighter, and less expensive than current systems.
The need in the art is addressed by the novel analog-to-digital converter (ADC) and direct digital synthesizer (DDS) architectures of the present invention. The novel ADC architecture includes a first circuit for receiving an input signal; a second circuit for setting a predetermined number of thresholds using a predetermined number of preamplifiers with weighted unit current sources in each of the preamplifier outputs; and a third circuit for comparing the input to the thresholds. The novel active offset method of the present invention removes the R-C time constant associated with the resistive ladder of conventional ADCs and provides the ability to easily trim individual thresholds without the need for trimmable resistors. In the preferred embodiment, the ADC includes trimmable current sources.
In the best mode, the ADC of the present invention incorporates an improved comparator circuit. The novel comparator includes split load resistors to increase the acquisition time and reduce the regeneration time constant, emitter follower buffers on the latch pair transistors to reduce the capacitive loading on the regeneration node, and cascode transistors coupled to the load resistors to eliminate the output loading effects from the regeneration node. All of these improvements allow a faster acquisition time and regeneration time constant to be on the order of the forward transit time in the transistor, which is a theoretical limit.
When implemented as an Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals, the ADAM Application Specific Integrated Circuit (ASIC) may integrate a complete receiver/exciter function on a monolithic silicon germanium (SiGe) device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. Thus, the teachings disclosed herein provide for improved analog-to-digital converter (ADC) operation via a novel active offset comparison methodology.
The novel DDS architecture overcomes the existing accuracy and dynamic limitations of digital-to-analog converter (DAC) structures through the ability to digitally trim out differential nonlinearities of the converter. Additionally, digital algorithms are implemented which address the limitations that transistor self-heating has had on converter dynamic range.